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lamazavr
Сообщения: 28

Сообщение lamazavr » 11 апр 2015, 11:21

Добрый день, работаю над проектом на Cyclone IV E EP4CE22E22I7.
Добавил в проект несколько простых модулей (остальные пока пустые), и PLL через мегафункцию квартуса.
Но вот не задача, сборка осуществляется успешно, но использовано только 32 пина, остальные показатели по 0.
В чем может быть проблема?
Железки пока нет, проверить работу не могу. Есть опасения, что беда будет :( .
Вывод:

Код: Выделить всё

Info: *******************************************************************
Info: Running Quartus II 32-bit Analysis & Synthesis
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:14 2015
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:14 2015
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off NVSAM -c NVSAM
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (12021): Found 1 design units, including 1 entities, in source file main.bdf
   Info (12023): Found entity 1: main
   Info (12023): Found entity 1: main
Info (12021): Found 1 design units, including 1 entities, in source file mcbsp.bdf
   Info (12023): Found entity 1: mcbsp
   Info (12023): Found entity 1: mcbsp
Info (12021): Found 2 design units, including 1 entities, in source file control_reg.vhd
   Info (12022): Found design unit 1: control_reg-arch
   Info (12023): Found entity 1: control_reg
   Info (12022): Found design unit 1: control_reg-arch
   Info (12023): Found entity 1: control_reg
Info (12021): Found 2 design units, including 1 entities, in source file cs_mux.vhd
   Info (12022): Found design unit 1: cs_mux-arh
   Info (12023): Found entity 1: cs_mux
   Info (12022): Found design unit 1: cs_mux-arh
   Info (12023): Found entity 1: cs_mux
Info (12021): Found 1 design units, including 1 entities, in source file async_port.bdf
   Info (12023): Found entity 1: async_port
   Info (12023): Found entity 1: async_port
Info (12021): Found 4 design units, including 2 entities, in source file clkctrl.vhd
   Info (12022): Found design unit 1: clkctrl_altclkctrl_7ji-RTL
   Info (12022): Found design unit 2: clkctrl-RTL
   Info (12023): Found entity 1: clkctrl_altclkctrl_7ji
   Info (12023): Found entity 2: clkctrl
   Info (12022): Found design unit 1: clkctrl_altclkctrl_7ji-RTL
   Info (12022): Found design unit 2: clkctrl-RTL
   Info (12023): Found entity 1: clkctrl_altclkctrl_7ji
   Info (12023): Found entity 2: clkctrl
Info (12021): Found 2 design units, including 1 entities, in source file async_ports_regs.vhd
   Info (12022): Found design unit 1: async_port_reg-arch
   Info (12023): Found entity 1: async_port_reg
   Info (12022): Found design unit 1: async_port_reg-arch
   Info (12023): Found entity 1: async_port_reg
Info (12021): Found 2 design units, including 1 entities, in source file sync_regs.vhd
   Info (12022): Found design unit 1: sync_reg-arch
   Info (12023): Found entity 1: sync_reg
   Info (12022): Found design unit 1: sync_reg-arch
   Info (12023): Found entity 1: sync_reg
Info (12127): Elaborating entity "main" for the top level hierarchy
Info (12128): Elaborating entity "mcbsp" for hierarchy "mcbsp:inst1"
Warning (275043): Pin "CS" is missing source
Warning (275043): Pin "WE" is missing source
Warning (275043): Pin "OE" is missing source
Warning (275043): Pin "ADDR[0..15]" is missing source
Warning (275043): Pin "DATA[0..15]" is missing source
Warning (275009): Pin "DATA_IN" not connected
Info (12128): Elaborating entity "async_port" for hierarchy "async_port:inst5"
Warning (275043): Pin "DATA_OUT[0..15]" is missing source
Warning (275009): Pin "CLK" not connected
Warning (275009): Pin "OE" not connected
Warning (275009): Pin "WE" not connected
Warning (275009): Pin "ADDR" not connected
Warning (275009): Pin "async_ports_cs" not connected
Warning (275009): Pin "DATA_IN" not connected
Warning (275009): Pin "recv_buffers_cs" not connected
Warning (275009): Pin "transiver_buffers_cs1" not connected
Warning (12125): Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
   Info (12022): Found design unit 1: pll-SYN
   Info (12023): Found entity 1: pll
   Info (12022): Found design unit 1: pll-SYN
   Info (12023): Found entity 1: pll
Info (12128): Elaborating entity "pll" for hierarchy "pll:inst4"
Info (12128): Elaborating entity "altpll" for hierarchy "pll:inst4|altpll:altpll_component"
Info (12130): Elaborated megafunction instantiation "pll:inst4|altpll:altpll_component"
Info (12133): Instantiated megafunction "pll:inst4|altpll:altpll_component" with the following parameter:
   Info (12134): Parameter "bandwidth_type" = "AUTO"
   Info (12134): Parameter "clk0_divide_by" = "12"
   Info (12134): Parameter "clk0_duty_cycle" = "50"
   Info (12134): Parameter "clk0_multiply_by" = "25"
   Info (12134): Parameter "clk0_phase_shift" = "0"
   Info (12134): Parameter "clk1_divide_by" = "48"
   Info (12134): Parameter "clk1_duty_cycle" = "50"
   Info (12134): Parameter "clk1_multiply_by" = "25"
   Info (12134): Parameter "clk1_phase_shift" = "0"
   Info (12134): Parameter "compensate_clock" = "CLK0"
   Info (12134): Parameter "inclk0_input_frequency" = "20833"
   Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
   Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"
   Info (12134): Parameter "lpm_type" = "altpll"
   Info (12134): Parameter "operation_mode" = "NORMAL"
   Info (12134): Parameter "pll_type" = "AUTO"
   Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
   Info (12134): Parameter "port_areset" = "PORT_USED"
   Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
   Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
   Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
   Info (12134): Parameter "port_inclk0" = "PORT_USED"
   Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
   Info (12134): Parameter "port_locked" = "PORT_UNUSED"
   Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
   Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
   Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
   Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
   Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
   Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
   Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
   Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
   Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk0" = "PORT_USED"
   Info (12134): Parameter "port_clk1" = "PORT_USED"
   Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
   Info (12134): Parameter "width_clock" = "5"
   Info (12134): Parameter "bandwidth_type" = "AUTO"
   Info (12134): Parameter "clk0_divide_by" = "12"
   Info (12134): Parameter "clk0_duty_cycle" = "50"
   Info (12134): Parameter "clk0_multiply_by" = "25"
   Info (12134): Parameter "clk0_phase_shift" = "0"
   Info (12134): Parameter "clk1_divide_by" = "48"
   Info (12134): Parameter "clk1_duty_cycle" = "50"
   Info (12134): Parameter "clk1_multiply_by" = "25"
   Info (12134): Parameter "clk1_phase_shift" = "0"
   Info (12134): Parameter "compensate_clock" = "CLK0"
   Info (12134): Parameter "inclk0_input_frequency" = "20833"
   Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
   Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pll"
   Info (12134): Parameter "lpm_type" = "altpll"
   Info (12134): Parameter "operation_mode" = "NORMAL"
   Info (12134): Parameter "pll_type" = "AUTO"
   Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
   Info (12134): Parameter "port_areset" = "PORT_USED"
   Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
   Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
   Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
   Info (12134): Parameter "port_inclk0" = "PORT_USED"
   Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
   Info (12134): Parameter "port_locked" = "PORT_UNUSED"
   Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
   Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
   Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
   Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
   Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
   Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
   Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
   Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
   Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
   Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk0" = "PORT_USED"
   Info (12134): Parameter "port_clk1" = "PORT_USED"
   Info (12134): Parameter "port_clk2" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk3" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
   Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
   Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
   Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
   Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pll_altpll.v
   Info (12023): Found entity 1: pll_altpll
   Info (12023): Found entity 1: pll_altpll
Info (12128): Elaborating entity "pll_altpll" for hierarchy "pll:inst4|altpll:altpll_component|pll_altpll:auto_generated"
Info (12128): Elaborating entity "clkctrl" for hierarchy "clkctrl:inst7"
Info (12128): Elaborating entity "clkctrl_altclkctrl_7ji" for hierarchy "clkctrl:inst7|clkctrl_altclkctrl_7ji:clkctrl_altclkctrl_7ji_component"
Info (12128): Elaborating entity "cs_mux" for hierarchy "cs_mux:inst2"
Info (12128): Elaborating entity "control_reg" for hierarchy "control_reg:inst"
Warning (10540): VHDL Signal Declaration warning at control_reg.vhd(27): used explicit default value for signal "VerSoft" because signal was never assigned a value
Warning (14284): Synthesized away the following node(s):
   Warning (14285): Synthesized away the following PLL node(s):
      Warning (14320): Synthesized away node "pll:inst4|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]"
   Warning (14285): Synthesized away the following PLL node(s):
      Warning (14320): Synthesized away node "pll:inst4|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]"
      Warning (14320): Synthesized away node "pll:inst4|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]"
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
Warning (21074): Design contains 1 input pin(s) that do not drive logic
   Warning (15610): No output dependent on input pin "CLK_IN"
   Warning (15610): No output dependent on input pin "CLK_IN"
Info (21057): Implemented 31 device resources after synthesis - the final resource count might be different
   Info (21058): Implemented 16 input pins
   Info (21059): Implemented 15 output pins
   Info (21058): Implemented 16 input pins
   Info (21059): Implemented 15 output pins
Info: Quartus II 32-bit Analysis & Synthesis was successful. 0 errors, 23 warnings
   Info: Peak virtual memory: 282 megabytes
   Info: Processing ended: Sat Apr 11 11:19:25 2015
   Info: Elapsed time: 00:00:11
   Info: Total CPU time (on all processors): 00:00:11
   Info: Peak virtual memory: 282 megabytes
   Info: Processing ended: Sat Apr 11 11:19:25 2015
   Info: Elapsed time: 00:00:11
   Info: Total CPU time (on all processors): 00:00:11
Info: *******************************************************************
Info: Running Quartus II 32-bit Fitter
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:27 2015
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:27 2015
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off NVSAM -c NVSAM
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (119006): Selected device EP4CE22E22I7 for design "NVSAM"
Info (21077): Low junction temperature is -40 degrees C
Info (21077): High junction temperature is 100 degrees C
Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
   Info (176445): Device EP4CE10E22A7 is compatible
   Info (176445): Device EP4CE10E22C7 is compatible
   Info (176445): Device EP4CE10E22I7 is compatible
   Info (176445): Device EP4CE6E22A7 is compatible
   Info (176445): Device EP4CE6E22C7 is compatible
   Info (176445): Device EP4CE6E22I7 is compatible
   Info (176445): Device EP4CE15E22C7 is compatible
   Info (176445): Device EP4CE15E22I7 is compatible
   Info (176445): Device EP4CE22E22A7 is compatible
   Info (176445): Device EP4CE22E22C7 is compatible
   Info (176445): Device EP4CE10E22A7 is compatible
   Info (176445): Device EP4CE10E22C7 is compatible
   Info (176445): Device EP4CE10E22I7 is compatible
   Info (176445): Device EP4CE6E22A7 is compatible
   Info (176445): Device EP4CE6E22C7 is compatible
   Info (176445): Device EP4CE6E22I7 is compatible
   Info (176445): Device EP4CE15E22C7 is compatible
   Info (176445): Device EP4CE15E22I7 is compatible
   Info (176445): Device EP4CE22E22A7 is compatible
   Info (176445): Device EP4CE22E22C7 is compatible
Info (169124): Fitter converted 2 user pins into dedicated programming pins
   Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
   Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
   Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location 6
   Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location 8
Info (169141): DATA[0] dual-purpose pin not reserved
Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
Critical Warning (169085): No exact pin location assignment(s) for 1 pins of 31 total pins
   Info (169086): Pin FSX not assigned to an exact location on the device
   Info (169086): Pin FSX not assigned to an exact location on the device
Info (332104): Reading SDC File: 'NVSAM.sdc'
Info (332151): Clock uncertainty calculation is delayed until the next update_timing_netlist call
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
Info (332111): Found 1 clocks
   Info (332111):   Period   Clock Name
   Info (332111): ======== ============
   Info (332111):   20.833       CLK_IN
   Info (332111):   Period   Clock Name
   Info (332111): ======== ============
   Info (332111):   20.833       CLK_IN
Info (176233): Starting register packing
Info (176235): Finished register packing
   Extra Info (176219): No registers were packed into other blocks
   Extra Info (176219): No registers were packed into other blocks
Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
   Info (176211): Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)
      Info (176212): I/O standards used: 2.5 V.
   Info (176211): Number of I/O pins in group: 1 (unused VREF, 2.5V VCCIO, 0 input, 1 output, 0 bidirectional)
      Info (176212): I/O standards used: 2.5 V.
      Info (176212): I/O standards used: 2.5 V.
Info (176215): I/O bank details before I/O pin placement
   Info (176214): Statistics of I/O banks
      Info (176213): I/O bank number 1 does not use VREF pins and has 2.5V VCCIO pins. 5 total pin(s) used --  3 pins available
      Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  7 pins available
      Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  10 pins available
      Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  10 pins available
      Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  9 pins available
      Info (176213): I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  2 pins available
      Info (176213): I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  4 pins available
      Info (176213): I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  3 pins available
   Info (176214): Statistics of I/O banks
      Info (176213): I/O bank number 1 does not use VREF pins and has 2.5V VCCIO pins. 5 total pin(s) used --  3 pins available
      Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  7 pins available
      Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  10 pins available
      Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  10 pins available
      Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  9 pins available
      Info (176213): I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  2 pins available
      Info (176213): I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  4 pins available
      Info (176213): I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  3 pins available
      Info (176213): I/O bank number 1 does not use VREF pins and has 2.5V VCCIO pins. 5 total pin(s) used --  3 pins available
      Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  7 pins available
      Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  10 pins available
      Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used --  10 pins available
      Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used --  9 pins available
      Info (176213): I/O bank number 6 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  2 pins available
      Info (176213): I/O bank number 7 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  4 pins available
      Info (176213): I/O bank number 8 does not use VREF pins and has 2.5V VCCIO pins. 8 total pin(s) used --  3 pins available
Info (171121): Fitter preparation operations ending: elapsed time is 00:00:01
Info (170189): Fitter placement preparation operations beginning
Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00
Info (170191): Fitter placement operations beginning
Info (170137): Fitter placement was successful
Info (170192): Fitter placement operations ending: elapsed time is 00:00:00
Info (170193): Fitter routing operations beginning
Info (170195): Router estimated average interconnect usage is 0% of the available device resources
   Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y0 to location X42_Y10
   Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X32_Y0 to location X42_Y10
Info (170194): Fitter routing operations ending: elapsed time is 00:00:00
Info (170199): The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time.
   Info (170201): Optimizations that may affect the design's routability were skipped
   Info (170200): Optimizations that may affect the design's timing were skipped
   Info (170201): Optimizations that may affect the design's routability were skipped
   Info (170200): Optimizations that may affect the design's timing were skipped
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info: Quartus II 32-bit Fitter was successful. 0 errors, 4 warnings
   Info: Peak virtual memory: 335 megabytes
   Info: Processing ended: Sat Apr 11 11:19:48 2015
   Info: Elapsed time: 00:00:21
   Info: Total CPU time (on all processors): 00:00:15
   Info: Peak virtual memory: 335 megabytes
   Info: Processing ended: Sat Apr 11 11:19:48 2015
   Info: Elapsed time: 00:00:21
   Info: Total CPU time (on all processors): 00:00:15
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:50 2015
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:50 2015
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off NVSAM -c NVSAM
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:50 2015
   Info: Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition
   Info: Processing started: Sat Apr 11 11:19:50 2015
Info: Command: quartus_sta NVSAM -c NVSAM
Info: qsta_default_script.tcl version: #1
Warning (20028): Parallel compilation is not licensed and has been disabled
Info (21077): Low junction temperature is -40 degrees C
Info (21077): High junction temperature is 100 degrees C
Info (332104): Reading SDC File: 'NVSAM.sdc'
Info (332151): Clock uncertainty calculation is delayed until the next update_timing_netlist call
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 100C Model
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 16.833
   Info (332119):     Slack End Point TNS Clock
   Info (332119): ========= ============= =====================
   Info (332119):    16.833         0.000 CLK_IN
   Info (332119):     Slack End Point TNS Clock
   Info (332119): ========= ============= =====================
   Info (332119):    16.833         0.000 CLK_IN
Info: Analyzing Slow 1200mV -40C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (115031): Writing out detailed assembly data for power analysis
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No fmax paths to report
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (115030): Assembler is generating device programming files
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 16.833
   Info (332119):     Slack End Point TNS Clock
   Info (332119): ========= ============= =====================
   Info (332119):    16.833         0.000 CLK_IN
   Info (332119):     Slack End Point TNS Clock
   Info (332119): ========= ============= =====================
   Info (332119):    16.833         0.000 CLK_IN
Info: Analyzing Fast 1200mV -40C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332154): The derive_clock_uncertainty command did not apply clock uncertainty to any clock-to-clock transfers.
Info (332140): No Setup paths to report
Info (332140): No Hold paths to report
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 16.833
   Info (332119):     Slack End Point TNS Clock
   Info (332119): ========= ============= =====================
   Info (332119):    16.833         0.000 CLK_IN
   Info (332119):     Slack End Point TNS Clock
   Info (332119): ========= ============= =====================
   Info (332119):    16.833         0.000 CLK_IN
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
   Info: Peak virtual memory: 274 megabytes
   Info: Processing ended: Sat Apr 11 11:20:15 2015
   Info: Elapsed time: 00:00:25
   Info: Total CPU time (on all processors): 00:00:10
   Info: Peak virtual memory: 274 megabytes
   Info: Processing ended: Sat Apr 11 11:20:15 2015
   Info: Elapsed time: 00:00:25
   Info: Total CPU time (on all processors): 00:00:10
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 1 warning
   Info: Peak virtual memory: 272 megabytes
   Info: Processing ended: Sat Apr 11 11:20:16 2015
   Info: Elapsed time: 00:00:26
   Info: Total CPU time (on all processors): 00:00:11
   Info: Peak virtual memory: 272 megabytes
   Info: Processing ended: Sat Apr 11 11:20:16 2015
   Info: Elapsed time: 00:00:26
   Info: Total CPU time (on all processors): 00:00:11
Info (293026): Skipped module PowerPlay Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER
Info (293000): Quartus II Full Compilation was successful. 0 errors, 28 warnings

Partokus
Сообщения: 1

Сообщение Partokus » 10 мар 2018, 23:57

проверьте внимательно код ещё раз на ошбики, связаны ли входные сигналы с выходными, то есть все ли выходные пины( в том числе промежуточные) включены в код

Вернуться в «Микроконтроллеры и ПЛИС»



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