Страничка эмбеддера, Форум

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module fulladder (c, a, b, Carry_Out, Out);
input c, a, b;
output reg Carry_Out, Out;
always @*
begin
//assign preOut = a ^ b;
Out = (a ^ b) ^ c;
Carry_Out = a & b | a & c | b & c;
end
endmodule

module Major (
	a, 
	Carry_Out1, Out1, Carry_Out2, Out2,
	Carry_Out3, Out3, Carry_Out4, Out4,
	Carry_Out5, Out5, Carry_Out6, Out6,
	Carry_Out7, Out7, Carry_Out8, Out8,
	Carry_Out9, Out9, Carry_Out10, Out10,
	Carry_Out11, Out11
	);
    input [12:0]a;
    output Carry_Out1, Out1, Carry_Out2, Out2,
	Carry_Out3, Out3, Carry_Out4, Out4,
	Carry_Out5, Out5, Carry_Out6, Out6,
	Carry_Out7, Out7, Carry_Out8, Out8,
	Carry_Out9, Out9, Carry_Out10, Out10,
	Carry_Out11, Out11;


fulladder ADD1 (a[0], a[1], a[2],                        Out1, Carry_Out1);
fulladder ADD2 (a[4], a[5], a[6],                        Out2, Carry_Out2);
fulladder ADD3 (a[7], a[8], a[9],                        Out3, Carry_Out3);
fulladder ADD4 (a[10], a[11], a[12],                     Out4, Carry_Out4);

fulladder ADD5 (a[3], Out1, Out2,                        Out5, Carry_Out5);
fulladder ADD6 (Carry_Out5, Carry_Out1, Carry_Out2,      Out6, Carry_Out6);
fulladder ADD7 (1'b1, Out3, Out4,                        Out7, Carry_Out7);
fulladder ADD8 (Carry_Out7, Carry_Out3, Carry_Out4,      Out8, Carry_Out8);

fulladder ADD9 (1'b0, Out5, Out7,                        Out9, Carry_Out9);
fulladder ADD10 (Carry_Out9, Out6, Out8,                 Out10, Carry_Out10);
fulladder ADD11 (Carry_Out10, Carry_Out6, Carry_Out8,    Out11, Carry_Out11);
endmodule 

Code: Select all

`timescale 1ns / 10ps
module tb_majority;

//inputs
reg [12:0] a;
//outputs
wire Carry_Out1, Out1, Carry_Out2, Out2,
	 Carry_Out3, Out3, Carry_Out4, Out4,
	 Carry_Out5, Out5, Carry_Out6, Out6,
	 Carry_Out7, Out7, Carry_Out8, Out8,
	 Carry_Out9, Out9, Carry_Out10, Out10,
	 Carry_Out11, Out11;

Major uut (
	.a(a), 
	.Carry_Out1(Carry_Out1),   .Out1(Out1), 
	.Carry_Out2(Carry_Out2),   .Out2(Out2),
	.Carry_Out3(Carry_Out3),   .Out3(Out3),
	.Carry_Out4(Carry_Out4),   .Out4(Out4),
	.Carry_Out5(Carry_Out5),   .Out5(Out5),
	.Carry_Out6(Carry_Out6),   .Out6(Out6),
	.Carry_Out7(Carry_Out7),   .Out7(Out7),
	.Carry_Out8(Carry_Out8),   .Out8(Out8),
	.Carry_Out9(Carry_Out9),   .Out9(Out9),
	.Carry_Out10(Carry_Out10), .Out10(Out10),
	.Carry_Out11(Carry_Out11), .Out11(Out11)
	);

integer k;

initial 
begin
a = 0;
for (k=0; k<8192; k=k+1)
  #5 a = k;

#10000 $finish;

end

endmodule