Страничка эмбеддера, Форум

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module Predikter
	(
     input wire clk,
     output wire out1,
	  output wire out2
    );

gen g_module (.clk(clk), .out(out1));
dig_pred d_module (.clk(clk), .sgn(out1), .out(out2));

endmodule

//----------------------------------------------------------------

module gen
	(
     input wire clk,
     output wire out
    );

localparam 		W = 6;
	 
reg[W:0] cnt = 0;

always @ (posedge clk) cnt <= cnt + 1;

assign out = cnt[W];

endmodule

//----------------------------------------------------------------

module dig_pred
	(
     input wire clk,
	  input wire sgn,
	 
	  output reg out
     );

localparam 		phase = 10;
				
reg[8:0]			pos_cnt = 0,
					neg_cnt = 0;

always @ (posedge clk)
	begin
		if (sgn)
			begin
				pos_cnt <= pos_cnt + 1;
				
				if (neg_cnt != 0)
					begin
						if (neg_cnt != phase) neg_cnt <= neg_cnt - 1;
						else
							begin
								out <= 0;
								neg_cnt <= 0;
							end
					end
			end
		else
			begin
				neg_cnt <= neg_cnt + 1;
				
				if (pos_cnt != 0)
					begin
						if (pos_cnt != phase) pos_cnt <= pos_cnt - 1;
						else
							begin
								out <= 1;
								pos_cnt <= 0;
							end
					end
			end
	end

endmodule

//----------------------------------------------------------------

/* 
set_location_assignment PIN_1 -to clk
set_location_assignment PIN_100 -to in1
set_location_assignment PIN_92 -to in2
set_location_assignment PIN_84 -to in3
set_location_assignment PIN_76 -to in4
set_location_assignment PIN_75 -to out1
set_location_assignment PIN_68 -to out2
set_location_assignment PIN_58 -to out3
set_location_assignment PIN_51 -to out4
*/